CMOS 6T SRAM cell

CMOS 6T SRAM cell 1.0

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Switch-level demonstration of the typical six-transistor SRAM storage cell.
 
1.0 (See all)
University of Hamburg

A switch-level demonstration of the typical six-transistor SRAM storage cell.
Click the input switches of the type the 'd' bindkey to control the DATAIN data input value, 'e' to enable the bit line tristate drivers, and 'w' to control the word line.

The memory cell shown here forms the basis for most static random-access memories in CMOS technology. It uses six transistors to store and access one bit.

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