FastFlow

FastFlow is a C++ parallel programming framework aimed at simplifying the development of efficient applications for multi-core platforms.

The key vision of FastFlow is that ease-of-development and runtime efficiency can both be achieved by raising the abstraction level of the design phase, thus providing developers with a suitable set of parallel programming patterns that can be efficiently compiled onto the target platforms.
FastFlow is conceptually designed as a stack of layers that progressively abstract the shared memory parallelism at the level of cores up to the definition of useful programming constructs supporting structured parallel programming on cache-coherent shared memory multi- and many-core architectures and clusters of them (see http://di.unito.it/fastflow ).
These architectures include commodity, homogeneous, multi-core systems such as Intel core, AMD K10, etc. FastFlow natively supports stream parallelism since it implements parallelism patterns as data-flow graphs - so-called streaming networks.
The run-time support of the FastFlow framework provides an efficient implementation of Single-Producer-Single-Consumer (SPSC) FIFO queues. FastFlow SPSC queues are lock-free, wait-free, and do not use interlocked operations. The SPSC queue is primarily used as synchronization mechanism for memory pointers in a consumer-producer fashion. The next tier up extends one-to-one queues to many-to-many synchronizations and data flows, which are implemented using only SPSC queues and arbiter threads, thus providing lock-free arbitrary streaming networks that requires few or no memory barriers, and thus few cache invalidations.
The upper layer, i.e. high-level programming, provides a programming framework based on parallel patterns. In particular, FastFlow provides FARM, FARM-WITH-FEEDBACK (i.e. D&C), PIPELINE, MAP and REDUCE patterns, and supports their arbitrary nesting and composition. The FastFlow pattern set can be further extended by building new C++ templates.
What's new in this version:
Automatic core pinning. New patterns (map, reduce). Improved performance. Support for clusters of SMPs. Many improvements and fixes.